Using constrained scan cells to test integrated circuits

ABSTRACT

Various new and non-obvious apparatus and methods for testing an integrated circuit are disclosed. In one exemplary embodiment, a control point is selected in an integrated circuit design. Scan cells in the integrated circuit design are identified that can be loaded with a set of fixed values in order to propagate a desired test value to the control point. The integrated circuit design is modified to include circuit components configured to load the scan cells in the integrated circuit design with the set of fixed values during a test phase. The one or more scan cells may be identified by justifying the control point to the scan cells, thereby determining values that the scan cells must output in order to drive the control point to the desired test value. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or computer-readable design information for any of the disclosed apparatus are also disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.60/510,641, filed Oct. 10, 2003, which is hereby incorporated byreference.

TECHNICAL FIELD

This invention relates generally to the testing of circuits for faults.More particularly, this invention relates to a method and apparatus forconstraining scan cells in a circuit under test to improve itstestability.

BACKGROUND

The very large scale integrated (VLSI) circuits fabricated todaytypically contain hundreds of thousands of circuit elements. Testingthese complex circuits to isolate faulty circuits from fault-freecircuits has become increasingly difficult because of theinaccessibility of internal circuit elements and the elements'interdependencies. Furthermore, as the number of possible test pathsthrough a circuit rises at 2^(n), where n is the number of circuitelements, efficient testing will continue to increase in difficulty asthe density of these circuits continues to grow.

To test a circuit, a set of test vectors, or patterns, must bedeveloped. The circuit is simulated without faults and the test patternsare applied to determine the circuit's expected response to the patternsat its primary outputs. The circuit is then simulated with faults andthe test patterns again applied to determine if there is a change in theexpected response to any pattern at the outputs. A fault that does notcause a change in the expected (fault free) response is an undetectedfault. A test procedure desirably detects a high percentage of faults,and thus should have a minimum of undetected faults.

One common method of developing tests employs external automated testequipment (ATE). In this method, an automatic test pattern generator(ATPG) is used which, given a circuit and fault model, generates a setof test patterns designed to detect close to 100% of the circuit'sfaults. These deterministic test patterns are then compressed and storedin a tester. During testing, they are decompressed and loaded into theprimary inputs of the circuit under test (CUT). Faults are detected bycomparing the response of the circuit to the expected response. Althoughdeterministic ATPG can detect close to 100% of faults, it requiresenormous resources to generate and store the test patterns required forcomplex VLSI circuits. Furthermore, interactions between the externaltester and elements in the CUT create their own set of potential errors.

To counter these problems, built-in self-test (BIST) methods have beendeveloped that move the test pattern generation and output responseanalysis from an external source onto the chip itself. The core of theBIST technology is that rather than using a defined set of test patternsspecifically defined to detect a known set of faults, a pseudo-randompattern generator (PRPG), generally a linear feedback shift register(LFSR), on the chip itself generates pseudo-random patterns which arethen used to detect faults. On-chip output response analysis istypically performed by a multiple-input-shift-register (MISR), a circuitthat compacts the output response and generates a signature forcomparison with the signature of a fault-free circuit.

Although pseudo-random pattern generation is simple, this method rarelyachieves the close-to 100% fault detection achieved by ATPG, as thereare almost always faults that require very specific patterns to test;these patterns often take many, many cycles to be automaticallygenerated, thereby elevating the cost of test application and faultsimulation beyond acceptable levels.

To tackle the problem of pseudo-random-pattern resistance, manytechniques have been proposed, which, generally speaking, can beclassified into two categories: changing the attributes of thepseudo-random patterns, or physically modifying the CUT.

The first category consists of techniques for modifying thepseudo-random patterns to provide better fault coverage. Some of thesemodification methods include reseeding, weighted random testing, andpattern mapping. In reseeding, deterministic test patterns arecompressed and encoded as seeds for a PRPG. These seeds then generatetest patterns known to find otherwise-undetectable faults. Weightedrandom testing uses mathematical methods to tweak the pseudo-randompatterns in ways that bias them toward detectingrandom-pattern-resistant faults by assigning weights to the valuescontained in specific scan cells, biasing their values towards “1” or“0”. Pattern mapping takes the set of patterns generated by the PRPG andtransforms them, using on-chip logic, into a new set of deterministicpatterns that provides the desired fault coverage. However, thesemethods are significantly more complicated than simple random patterngeneration and either require extra memory to store the seeds or weightsets, or require additional logic, all of which is expensive in terms ofarea overhead.

Another way of improving random pattern testability is through physicalmodification of the CUT. Test points, which include observation andcontrol points, are inserted at selected nodes of the CUT. A controlpoint—which forces a specific location in the circuit under test to aparticular signal value—can test for known undetected faults at a node(e.g., a logic gate), and can also test for otherwise undetectablefaults in the node's fanout cone. A control point is typically insertedby adding logic to the circuit. An observation point allows faults to betested that do not propagate to a CUT output, but can be observed at aspecific location within the CUT logic. Observation points—typicallyinserted by adding an additional output lead from the node—improve theobservability both of the output of an internal node and nodes in itsfanin cone.

One such method of selecting and inserting test points, multi-phase testpoint insertion (MTPI), partitions the testing into multiple phases, inwhich each phase includes testing for a progressively reduced set offaults. In the first phase, observation points are selected to capturethe detectable faults. Within each subsequent phase, a set of controlpoints are selected that, when added to the CUT logic, can findstill-undetected faults. While observation points help improve faultcoverage, control points can cause complicated changes in the circuitthat may not always improve the fault coverage and that also may causetiming degradations due to the additional logic inserted into criticalpaths of the core logic of the CUT.

SUMMARY

Various new and non-obvious apparatus and methods for testing anintegrated circuit using modified scan cells are disclosed. Thedisclosed exemplary apparatus and methods should not be construed aslimiting in any way. Instead, the present disclosure is directed towardnovel and non-obvious features and aspects of the various disclosedembodiments, alone and in various combinations and subcombinations withone another. The apparatus and methods are not limited to any specificaspect, feature, or combinations thereof, nor do the disclosed apparatusand methods require that any one or more specific advantages be presentor problems be solved.

In one disclosed embodiment, a control point is selected in anintegrated circuit design. One or more scan cells in the integratedcircuit design are identified that can be loaded with a set of fixedvalues in order to propagate a desired test value to the control point.The integrated circuit design is modified to include circuit componentsconfigured to load the scan cells in the integrated circuit design withthe set of fixed values during a test phase. In certain implementations,the functional paths of the integrated circuit design are unchangedafter the modification. The one or more scan cells may be identified byjustifying the control point to one or more scan cells, therebydetermining values that the scan cells must output in order to drive thecontrol point to the desired test value. In some implementations, acontrol point can be selected by performing a probabilistic faultsimulation of the integrated circuit design, identifying one or morenodes in the integrated circuit design where fault coverage is below aselected threshold, and designating an output of one of the identifiednodes as the control point. The set of fixed value with which the one ormore scan cells can be loaded is termed a justification cube. In someimplementations, the method may further includes identifying multiplejustification cube candidates for propagating the desire value to thecontrol point, calculating a performance parameter for a selectedjustification cube candidate (the performance parameter being indicativeof the fault detection probability of the selected justification cube),and evaluating the justification cube candidate based at least in parton the performance parameter. The performance parameter may becalculated, for example, by obtaining a signal and pattern probabilityassociated with the selected justification cube candidate (e.g., bysimulating faults in the integrated circuit design while applying thejustification cube candidate to corresponding scan cells), using thesignal and pattern probability to obtain a propagation profileindicative of the selected justification cube candidate's ability tolocate faults, and calculating the performance parameter using thepropagation profile. In certain implementations, if a justification-cubecandidate overlaps a previously chosen justification cube candidate, itis discarded. The method may further include identifying at least oneobservation point (a point in the integrated circuit design having avalue indicative of the existence of a downstream fault) in theintegrated circuit design.

In another embodiment, a method of testing an integrated circuit isdisclosed. In this embodiment, a test pattern is shifted into a scanchain comprising multiple scan cells, and, during a portion of theperiod of clock cycles, the inputs of one or more scan cells in the scanchain are overridden to load a set of known values into the scan chain.thereby modifying the test pattern. The modified test pattern may belaunched into the logic of the integrated circuit, thereby provoking atargeted fault at a control point. In some implementations, the act ofoverriding the inputs of the one or more scan cells is triggered by asignal generated on the integrated circuit (e.g., from a phase decoderon the integrated circuit). Furthermore, the overriding can be executedat least partially by logic coupled to the inputs of one or more of thescan cells. In some embodiments, the portion of the period of clockcycles when the scan cells are overridden is the last clock cycle of theperiod.

Another of the disclosed embodiments is a scan cell used for testinglogic in an integrated circuit. The scan cell of this embodimentcomprises a clocked element (e.g., a flip-flop) that inputs test-patterndata from a test-pattern-input path during a scan mode and inputs systemdata on a system-data path during an operational mode, respectively. Thescan cell also comprises test logic having an output coupled to thetest-pattern-input path and having inputs coupled to a scan path and oneor more scan-override paths. In this embodiment, the value on at leastone of the scan override paths controls the value on the test-patterninput path and is at least partially determined by test hardware (e.g.,a phase decoder and shift counter) located on the integrated circuit.The clocked element may be further configured to output data on adownstream functional path whose timing is unaffected by the test logic.In some implementations, the test logic is configured to output a logichigh value or a logic low value on the test-pattern-input path when ascan-override path has a logic high value.

Another disclosed embodiment is a method for designing a built-inself-test (BIST) architecture for a circuit under test (CUT). In thisembodiment, faults are simulated within the CUT (e.g., faults undetectedby pseudo-random patterns), and a control point candidate within thelogic of the CUT is identified which has a threshold probability ofprovoking a target fault when it has a specific logic value. The controlpoint candidate is justified to a corresponding set of one or more scancells in the CUT. The act of justifying comprises determining the valuesthat the corresponding set of one or more scan cells should output toforce the control point candidate to the specific logic value. Thejustified control point candidate is evaluated with respect to otherjustified control point candidates, and, based at least in part on theevaluation, at least one scan cell within the CUT is assigned to be aconstrained scan cell. The constrained scan cell can be configured toinput a set value during a predetermined test phase. The method mayfurther include selecting one or more observation points within thelogic of the CUT.

Another embodiment is a circuit which comprises circuit logic and one ormore scan chains. The scan chains are coupled to the circuit logic andare operable in at least two modes: a scan mode and an operational mode.This embodiment additionally comprises test logic that is coupled to ascan path of at least one scan cell and that is configured to load thescan cells with either a fixed value or a pseudo-random value during thescan mode. In certain implementations, the test logic is not directlycoupled to the circuit logic. The circuit may also include apseudo-random pattern generator (e.g., a linear feedback shift register(LFSR)) coupled to the test logic, which produces the pseudo-randomvalue. In certain implementations, the circuit also comprises a phasedecoder which is coupled to the test logic and which at least partiallyproduces the fixed value. In these implementations, the circuit may alsohave a shift counter which has an output signal that is logicallycoupled with an output signal of the phase decoder, the shift counterbeing configured to control when the fixed value is loaded by the testlogic into one of the scan cells. The shift counter may be configured,for example, to load the fixed value during a last shift cycle of thescan mode. The circuit may also include an observation point in thecircuit logic, the observation point having a value indicative of thepresence of a fault whose value does not otherwise propagate to circuitlogic outputs.

Any of the disclosed apparatus or methods may be designed or performedby a computer program, such as an electronic-design-automation (EDA)software tool comprising computer-executable instructions stored on acomputer-readable medium. Further, any of the disclosed apparatus (orapparatus designed by the disclosed methods) can be stored as circuitdesign information that is stored on a computer-readable medium. Thecircuit design information can be included in one or more datastructures or design databases that are updated or modified (e.g., on asingle computer or via a network). Accordingly, updated or modified datastructures or design databases storing circuit design information forany of the disclosed apparatus are also disclosed.

The foregoing and additional features and advantages of the disclosedembodiments will become more apparent from the following detaileddescription, which proceeds with reference to the following drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an exemplary computing environment as maybe used in connection with the disclosed technology.

FIG. 2 is a block diagram illustrating a conventional multi-phase testpoint insertion (MTPI) architecture.

FIG. 3 is a block diagram illustrating a conventional control pointimplementation.

FIG. 4 is a block diagram illustrating a representative embodiment ofthe disclosed constrained-scan-cell architecture.

FIG. 5 is a block diagram illustrating a portion of an exemplary scanchain.

FIG. 6 is a timing diagram of output signals from an embodiment of thedisclosed constrained-scan-cell architecture.

FIG. 7 is a block diagram illustrating a portion of the relationship ofscan cells to logic within the CUT.

FIG. 8 is a block diagram illustrating a conventional scan cell

FIG. 9A is a block diagram illustrating a first embodiment of aconstrained scan cell.

FIG. 9B is a block diagram illustrating a second embodiment of aconstrained scan cell.

FIG. 9C is a block diagram illustrating a third embodiment of aconstrained scan cell.

FIG. 10 is a graph of fault coverage of a four-phase test utilizing anembodiment of the disclosed architecture.

FIG. 11 is a flowchart illustrating an exemplary method for implementingconstrained-scan-cell selection using some of the disclosed principles.

FIG. 12 is a flowchart illustrating an exemplary method for implementingconstrained-scan-cell selection that extends some of the aspects of themethods shown in FIG. 11.

FIG. 13 is a flowchart illustrating an exemplary method for evaluatingcube candidates that extends some of the aspects of the methods shown inFIGS. 11 and 12.

FIG. 14 is a system diagram of a client/server network as may be used indesigning and/or implementing the disclosed constrained-scan-cellarchitecture.

FIG. 15 is a flowchart showing the creation of a database using, forexample, the network of FIG. 14.

DETAILED DESCRIPTION I. General Considerations

Disclosed below are representative embodiments of modified scan cellsand of an on-chip testing architecture utilizing such scan cells, aswell as methods for using and designing such embodiments that should notbe construed as limiting in any way. Instead, the present disclosure isdirected toward novel and nonobvious features and aspects of the variousdisclosed apparatus and methods, and their equivalents, alone and invarious combinations and subcombinations with one another. The inventionis not limited to any specific aspect or feature, or combinationthereof, nor do the disclosed methods and apparatus require that any oneor more specific advantages be present or problems be solved.

Although the operations of some of the disclosed methods and apparatusare described in a particular, sequential order for convenientpresentation, it should be understood that this manner of descriptionencompasses rearrangement, unless a particular ordering is required byspecific language set forth below. For example, operations describedsequentially may in some cases be rearranged or performed concurrently.Moreover, for the sake of simplicity, the attached figures may not showthe various ways in which the disclosed methods and apparatus can beused in conjunction with other methods and apparatus. Additionally, thedescription sometimes uses terms like “determine” and “evaluate” todescribe the disclosed methods. These terms are high-level abstractionsof the actual operations that are performed. The actual operations thatcorrespond to these terms will vary depending on the particularimplementation and are readily discernible by one of ordinary skill inthe art.

The disclosed embodiments can be implemented in a wide variety ofintegrated circuits or digital devices (e.g., application-specificintegrated circuits (ASICs), systems-on-a-chip (SoCs), or programmablelogic devices (PLDs) such as field programmable gate arrays (FPGAs),having a variety of different electrical components (e.g., digitalcomponents, analog components, or mixed-signal components).

Any of the apparatus described herein can be designed, verified, and/orsimulated using software that comprises computer-executable instructionsstored on one or more computer-readable media. Such software cancomprise, for example, an electronic-design-automation (EDA) softwaretool, such as a design, verification, or simulation tool. Similarly, anyof the methods described herein (e.g., constrained-scan cell selection,or testing using constrained scan cells) can be performed using softwarecomprising computer-executable instruction stored on one or morecomputer-readable media. Any such software can be executed on a singlecomputer or on a networked computer (e.g., via the Internet, a wide-areanetwork, a local-area network, a client-server network, or other suchnetwork). For clarity, only certain selected aspects of thesoftware-based implementations are described. Other details that arewell known in the art are omitted. For example, it should be understoodthat the disclosed technology is not limited to any specific computerlanguage, program, or computer. For the same reason, computer hardwareis not described in further detail.

Further, any of the disclosed apparatus can be stored as circuit designinformation on one or more computer-readable media. For example, one ormore data structures or databases containing design information (e.g., anetlist or an HDL file) can be created or updated to include designinformation for any of the disclosed constrained-scan-cellarchitectures. Similarly, a data structure or database containingresults from any of the disclosed constrained-scan-cell selectionprocedures can be created or updated and stored on one or morecomputer-readable media. Such data structures or databases can becreated or updated at a local computer or over a network (e.g., by aserver computer).

Referring to FIG. 1, an exemplary operating environment for performingembodiments of the disclosed technology is a computer system 100 with acomputer 102 that comprises at least one high speed processing unit(CPU) 104, in conjunction with a memory system 106, an input device 108,and an output device 110. These elements are interconnected by at leastone bus structure 112. Multiprocessor systems can also be used.

The illustrated CPU 104 is of familiar design and includes an ALU 114for performing computations, a collection of registers 116 for temporarystorage of data and instructions, and a control unit 118 for controllingoperation of the system 100. The CPU 104 may be a processor having anyof a variety of architectures now known or contemplated in the art.

The memory system 106 generally includes high-speed main memory 124,which has the form of a compute-readable medium such as random accessmemory (RAM) and read only memory (ROM) semiconductor devices, andsecondary storage 126, which has the form of long-term computer-readablemedia such as floppy disks, hard disks, tape, CD-ROM, flash memory, andother devices that store data using electrical, magnetic, optical, orother recording media. The memory system 106 also can include videodisplay memory, also known as screen memory 122, for displaying imagesthrough a display device. Those skilled in the art will recognize thatthe memory system 106 can comprise a variety of alternative componentshaving a variety of storage capacities.

The input and output devices 108, 110 also are familiar. The inputdevice 108 can comprise a keyboard, a mouse, a physical transducer(e.g., a microphone) and the like. The output device 110 can comprise adisplay, a printer, a transducer (e.g., a speaker), and the like. Somedevices, such as a network interface or a modem, can be used as inputand/or output devices.

As is known to those skilled in the art, the computer system 100 furtherincludes an operating system and at least one application program. Theoperating system is the set of software which controls the computersystem's operation and the allocation of resources. The applicationprogram is the set of software that performs a task desired by the user,using computer resources made available through the operating system.Both are resident in the illustrated memory system 106.

In accordance with the practices of persons skilled in the art ofcomputer programming, aspects of the disclosed technology are describedbelow with reference to acts and symbolic representations of operationsthat are performed by the computer system 100, unless indicatedotherwise. Such acts and operations are referred to as beingcomputer-executed or computer-implemented. It will be appreciated thatthe acts and symbolically represented operations include themanipulation by the CPU 104 of electrical signals representing databits. This manipulation causes a resulting transformation or reductionof the electrical signal representation of data bits at memory locationsin memory system 106 to thereby reconfigure or otherwise alter thecomputer system's operation, as well as other processing of signals. Thememory locations where data bits are maintained are physical locationsthat have particular electrical, magnetic, or optical propertiescorresponding to the data bits.

II. The MTPI Architecture in General

FIG. 2 illustrates a portion 200 of a circuit utilizing a conventionalmulti-phase test point insertion (MTPI) architecture. The illustratedMTPI architecture typically includes a test pattern generator 206, anoutput response analyzer 208, a phase decoder 204, and a pattern counter202. The test pattern generator 206 generates pseudo-random testpatterns that are fed into one or more scan chains 210. A common testpattern generator is a linear feedback shift register (LFSR). These testpatterns are then fed into the combinational logic of the circuit undertest (CUT) 212. The output response analyzer 208 (such as amultiple-input-shift-register (MISR) and related circuitry) analyzes theresponses of the combinational logic to the test patterns to detectfaults within the CUT 212. The applied test patterns are counted by thepattern counter 202. The phase decoder 204 responds to specified countsof the pattern counter 202 by generating a phase signal at its outputwhich is applied to control point test logic 218 inserted into to theCUT 212 and which serves to drive the control points C1 and C2 to afixed value during one or more test phases.

The phase decoder 204 generates a number of non-overlappingphase-control signals which corresponds to the number of test phasesused by the CUT during testing. The illustrated embodiment shows afour-phase system with three non-overlapping signals. At phase 0 of thisexample, all outputs are held low so that no control point is activated.For phases 1 through 3, one of the phase-control signals (ph_1, ph_2, orph_3, respectively) is held high in order to enable the correspondingcontrol points for that phase. Each phase thus enables a specific set ofcontrol points, changing the pseudo-random patterns in different waysand allowing different sets of faults to be detected.

In general, MTPI attempts to improve random pattern testability byplacing constant-value control points on a selected set of nodes withextremely low or high signal probability. Signal probability can bedefined as the probability that a node output assumes the value “1”during random testing. A node can be thought of as a logical unit—forexample, it may be one gate, or it may be several gates grouped togetherwith a single output. For a node with extremely low signalprobability—those that hold the value “0” for the majority of theapplied pseudo-random patterns—an OR gate can be used to force itsoutput value to “1”; likewise, an AND gate and an inverter can be usedto force the output of an extremely high signal probability node to thevalue “0”. In the illustrated embodiment a first node 214 (f_node) and asecond node 216 (g_node) produce a first signal 222 (f) and a secondsignal 224 (g), respectively, which are input into the control pointlogic 218, where they are coupled with the phase-control signals ph_1,ph_2, and ph_3.

FIG. 3 is a schematic block diagram showing one exemplary configurationfor the control point test logic 218 shown in FIG. 2. In the exemplarycontrol point test logic 218, the signal f from the node f_node is ANDedwith the inverse value of test signal 304 (f_test), which is produced byORing phase-control signal ph_1 and ph_2 produced by the phase decoder204. The value of f_test is “1” during test phases 1 and 2, forcing thecontrol point C1 to have the value “0” no matter what the value of f.However, during test phases 0 and 3 the value of f_test is “0”, so f'svalue is passed unchanged to control point C1. A similar analysis showsthat the value of test signal 308 (g_test) is “1” during test phases 2and 3, forcing the value of C2 to “1” regardless of g's value. Duringtest phases 0 and 1, g_test is “0”, allowing g's value to reach C2unchanged. Observation points (not shown) can be implemented asadditional fan-outs of the node being observed. Such fan-outs aredesirably fed into an output analyzer. It should be noted that theembodiments are not limited to tests of any specific number of phases,as more or fewer phases than the four illustrated in FIG. 2 can beimplemented.

In MTPI, control points and observation points are desirably selectedbased on probabilistic fault simulation (PFS). The objective of PFS isto determine, for each node, the list of faults that propagate to it andtheir associated detection probability. The information from the list offaults and the detection probability for each node may be called anode's “propagation profile.” To obtain a propagation profile, logicsimulation of a specified number of pseudo-random patterns can beperformed to obtain a signal and pattern probability at each node. Thepattern probability is a list of successive values held by the node andhow long each was held. The signal probability, the percentage of time anode's output value is “1” or “0”, is computed directly from the patternprobability.

Once the signal probability is obtained, the detection probability of atarget fault can be determined. Specifically, for each fault on thetarget fault list, forward-fault propagation, initially using thecorresponding signal probabilities, can be performed to compute thedetection probability of the fault at its fan-out region. A detectionthreshold is specified such that once a detection probability is lowerthan the detection threshold, the fault stops propagating forward. Theprobabilities of detecting faults in the target fault list that reachprimary outputs, scan cells, or observation points can be summed up todefine a criteria called “BPC” (benefit per cost), which indicates thedetectability of the target faults on the target fault list.

In MTPI, observation points are desirably selected during the first testphase, called here phase 0, and are preferably enabled through allphases of a test. According to one approach, fault simulation ofpseudo-random patterns is run first to exclude easy-to-detect faults.Probabilistic fault simulation is then performed to develop anundetected-fault list. Thus, each node is desirably associated with alist of undetected faults and its detection probabilities. Aset-covering method may then be applied to determine the set of nodesthat can capture the fault effects for a desired number, and morepreferably a maximal number, of undetected faults. These nodes may thenserve as observation points through all test phases.

At each of the following phases, in one MTPI embodiment, control pointsare selected sequentially. For example, probabilistic fault simulationmay be performed to obtain a propagation profile. Control-pointcandidates may then be determined by computing estimates E0/E1 for1/0-failing nodes. A 1/0-failing-node category may be assigned to anyone or more nodes with extreme-low or extreme-high signal probability.Estimates E0/E1 may denote the estimated number of faults that can beperturbed by virtually inserting a control point at a 1/0-failing node.In this exemplary approach, the 1/0-failing nodes with estimates E0/E1greater than a minimum acceptable value are identified as control-pointcandidates. The benefit of each control-point candidate can then becomputed. The best candidate is desirably selected and inserted into thenetlist. One or more additional iterations of control-point selectionmay be performed. Iterations may be continued until a desired faultcoverage is achieved or an abort limit reached.

By carefully picking test points, MTPI can achieve close to ATPGstuck-at coverage with very few test points. But, when control pointtest logic is inserted into the body of the CUT, it can cause timingdegradations due to the additional logic inserted into critical paths ofthe core logic of the CUT.

III. The Constrained-Scan-Cell Architecture in General

FIG. 4 is a schematic block diagram of a circuit 400 having incorporatedthereon a representative embodiment of the disclosed BIST architecture.In general, the illustrated embodiment utilizes existing scan cells inthe CUT 414 (which replace control points within the body of the CUT) totest pseudo-random pattern resistant faults. The exemplary architectureincludes a test pattern generator 410; an output analyzer 408, which mayitself incorporate a compactor or a MISR; a shift counter 404; and aphase decoder 402. The test pattern generator 410 (such as an LFSR)generates predetermined test patterns that are loaded into at least onescan chain 412 of the CUT 414. The test pattern generator 410 mayincorporate methods other than straight pseudo-random generation such asreseeding, weighted random testing, or pattern mapping. The outputresponse analyzer 408 (which might comprise one or more compactors, suchas MISRs and the like) analyzes the response of the circuit logic 415 tothe test patterns to detect faults within the circuit.

The scan chain 412 can be implemented according to a variety ofdifferent scan methodologies. For example, the scan chain may be part ofa full-scan or partial-scan design. Further, the scan cells in the scanchain 412 may vary from implementation to implementation. In theexemplary embodiments illustrated in FIGS. 9A to 9C below, for instance,the scan cells comprise MUX-D scan cells. However, in other embodiments,other types of scan cells or combinations thereof are utilized. Forexample, the scan cells may comprise level sensitive scan design (LSSD)based scan cells. Such scan cells can utilize, for example, pairs oflatches. Various other types and combinations of flip-flops, latches,and other such clocked elements can also be used.

The circuit 400 also includes a phase decoder 402 and a shift counter404 whose outputs, in the illustrated embodiment, are ANDed togetherthrough gates 406 to produce unique “test phase trigger signals” (alsoreferred to herein as “phase control signals”). When fed into test logic(T1, T2, and T3 in FIG. 4), the test phase trigger signals are used totrigger certain scan cells within the scan chain 412 such that they areloaded with a constant value during a specific test phase, therebyoverwriting the test pattern from the test pattern generator 410. In theembodiment illustrated in FIG. 4, for example, the test phase triggersignals comprise phase_cntl1 for test phase 1, phase_cntl2 for testphase 2, and phase_cntl3 for test phase 3.

In the exemplary embodiment shown in FIG. 4, the test phase triggersignals are generated in part from phase decoder signals, whichcorrespond to each test phase other than the first test phase (ph_1 fortest phase 1, ph_2 for test phase 2, and ph_3 for test phase 3, thefirst test phase being test phase 0). Phase decoder signals ph_1, ph_2,and ph_3 are ANDed at the gates 406 with the shift counter signal 418(last_shift) to produce the respective test phase trigger signals.Last_shift is an output signal from the shift counter 404 that, in oneexemplary embodiment, is high during the last shift cycle of scan-chainloading.

FIG. 6 shows an exemplary relationship of the last_shift signal and thesystem clock (CLK). In FIG. 6, last_shift is high at the rising edge ofthe clock cycle corresponding to the last shift cycle (shown as timeperiod T1 in FIG. 6). Thus, as is discussed below with respect to FIG.5, the test patterns being loaded into the scan chains of the CUT areoverwritten in part by values produced by the test logic, therebymodifying the test patterns. When the modified test patterns are loadedat this last shift cycle, they are also output (or launched) by the scanchains into the functional logic of the CUT. Before the rising edge ofthe next clock cycle, last_shift and Scan_en are disabled. Thus, at therising edge of the next clock cycle, the circuit response to themodified test patterns is captured within the scan cells. Scan_en isreasserted, and the circuit response is shifted out to be checked forfault conditions as the next set of test patterns are shifted in.

For the test logic to operate properly, the test phase trigger signalsmust reach the test logic of the constrained scan cells before the nextclock cycle. To make the test phase trigger signals not timing critical,the system clock may be suppressed such that last_shift stays high fortwo or more clock cycles. In such embodiments, enough time exists forthe test phase trigger signals to change to high and then back to lowduring testing without routing the test phase trigger signals as clocksignals.

Because the test phase trigger signals oscillate during testing, powerconsumption rises somewhat. Assuming that the shift clock frequency isf_(s) and that the maximum scan chain length is l, however, thefrequency of the phase-control signal is approximately f_(s)/l, which ismuch lower than the shift-clock frequency. Considering that the powerconsumption is generally a linear function of f² (i.e., the square offrequency), the power overhead induced by the test phase trigger signalsis relatively small.

In certain embodiments, the phase decoder 402 may be configured toproduce the test phase trigger signals without the shift counter (e.g.,counting logic may be incorporated into the phase decoder) or the phasesmay be triggered by some other predetermined event. Further, it shouldalso be noted that the illustrated embodiments are not limited to anyspecific number of test phases, as more or fewer test phases than thefour illustrated in FIG. 4 can be implemented.

IV. Exemplary Embodiments of Scan Chains Comprising Constrained ScanCells

FIG. 5 illustrates a scan chain 500 (such as scan chain 412 from FIG. 4)that has been modified to include a constrained scan cell according tothe disclosed technology. It should be understood that the six-scan-cellscan chain is simplified and for illustrative purposes only; typicalscan chains contain many more scan cells and a typical CUT contain manysuch scan chains. As opposed to MTPI, where the phase decoder stays highfor an entire test phase, in an exemplary embodiment of the disclosedtechnology, the phase decoder signal only stays high for the last shiftcycle of scan chain loading, as explained more fully below.

Scan chains typically operate in three separate phases during BISTtesting: a shift-in phase, where random test patterns are sequentiallyloaded into a scan chain; an operating phase, where the pattern input isshifted into core logic of the CUT, a response to the test pattern isproduced in the CUT and then the response is captured within the scanchain; and a shift-out phase, where the test pattern response is shiftedout to be compared with fault-free results. During the shift-in andshift-out phases (which typically occur concurrently), the scan cells ofa respective scan chain are configured to be sequentially coupled to oneanother such that the test patterns can be clocked into and out of thescan chains in much the same fashion as a shift register. During theoperating phase, the scan cells of a respective scan chain areconfigured to perform normally as sequential elements in a circuitdesign.

FIG. 5 illustrates the shift-in phase in the scan chain 500. Theexemplary scan chain 500 sequentially shifts in values from a testpattern generator, one shift per clock cycle, so that the scan chainwill shift six values in six clock cycles. In this example, the testpattern generator is assumed to be a PRPG (such as an LFSR). At 506,FIG. 5 shows the test pattern 504 (“0 0 1 0 0 1”) before being shiftedsequentially into the scan chain 500. The first test pattern value, a“1”, is illustrated as being shifted into the scan chain 500 during thefirst clock cycle 508. After the fifth clock cycle 510, the first fivecells in the scan chain have been loaded with the next test patternvalue. In the illustrated embodiment, test logic 514 constrains scancell 4 (SC₄) to a “1” during the last shift cycle. It can be seen thatthe value “0” residing in scan cell 3 (SC₃) after the fifth shift cycleshould be shifted into SC₄ during the last clock cycle. However, duringthe last shift clock cycle 512, the test logic 514 is triggered by thetest phase trigger signal at least partially determined by the phasedecoder. Consequently, the constrained value “1” is loaded into SC₄during the last shift cycle 512, overriding the “0” from the testpattern generator. During this clock cycle, the scan chain 500 launchesthe modified test pattern (“1 0 1 1 0 0” in the example shown) into thelogic of the circuit under test, thereby provoking at least onepreviously undetected fault.

In other embodiments, the phase decoder logic may shift the constrainedvalue into a set scan cell (such as scan cell 1) at a different clockcycle during the shift-in phase. For example, a constrained value (“1”or “0”) could be shifted into the scan cell 1 at the fifth clock cycle,and then shifted into scan cell 2 during the sixth and final clockcycle, overriding the test pattern value in the second scan cell. Suchvariations in when the constrained value is loaded may reduce theoverhead required to implement the constrained scan cells in aparticular circuit design.

FIG. 8 illustrates a conventional, unmodified scan cell 800 as can beused in a scan chain (such as scan chain 412 or 500). The scan cell 800comprises a sequential element 802 (e.g. a flip-flop or latch) with amultiplexer 804 placed in a data-input path 806 coupled to thesequential element's input (e.g., the D input of a D-type flip-flop). Ina system (or operating) mode, the multiplexer 804 can be set such thatthe scan cell 800 acts like an ordinary sequential element (here, aD-type flip-flop). In FIG. 8, for example, this is accomplished bysetting the signal on the scan-enable path (SE) to select thesystem-data path (D). During the shift-in or shift-out phase, themultiplexer 804 can be set such that the scan cell 800 operates in theso-called “scan mode” and forms one or more serially connected chains ofsequential elements that input test-pattern data generated from a testpattern generator (e.g., a PRPG). In FIG. 8, for example, scan mode canbe activated by setting the signal on the scan-enable path (SE) toselect the scan-input path (SI) (also known as the test-pattern inputpath), thereby inputting test-pattern data from the test patterngenerator or from an upstream scan cell into the scan cell 800. Thesequential element's output (e.g., the Q output of a D-type flip-flop)outputs data onto a path that may branch into a system-data path (Q) anda scan path (S). The system-data path (Q) is ordinarily coupled to logicwithin the CUT. The scan path (S) typically becomes the scan-input path(SI) of a downstream scan cell or is output to an appropriate primaryoutput or output analyzer of the CUT. In general, then, the scan path(S) is the path that carrying data through the scan chain.

To implement embodiments of the disclosed constrained-scan-cellarchitecture, one or more constrained scan cells can be utilized. Aconstrained scan cell can be constructed by adding test logic to thescan-input path of a conventional scan cell without affecting ormodifying the functional circuit paths downstream of the scan cell. Thetest logic can be configured to logically combine the scan-chain data onthe scan path with the signal on a scan-override path. The scan-overridepath typically carries a respective test phase trigger signal (e.g.,phase_cntl1, phase_cntl2, or phase_cntl3) such that the correspondingscan cell is constrained to a specific value when the scan-override pathhas a particular value. Because the test logic is implemented in thescan paths, rather than within the CUT itself (as in the conventionalMTPI architecture), it does not adversely impact timing during thefunctional operation of the CUT.

FIG. 9A shows a first exemplary type of constrained scan cell. Forillustrative purposes only, the scan cells in FIGS. 9A-9C comprise MUX-Dscan cells. It is understood, however, that other types of scan cell mayalso be used (e.g., scan cells constructed from latches or LSSD-basedscan cells). In FIG. 9A, a test phase trigger signal (here, phase_cntl1)on a scan-override path 908A and scan-chain data on a scan path 904A (S)from a previous scan cell or a test pattern generator are logicallycombined at a gate 906A, which implements an OR function. The output ofthe gate 906A is the scan-input path (SI) (or test-pattern input path)for the conventional scan cell 800A. In the illustrated embodiment, thevalue of phase_cntl1 is “1” during the last shift of scan chain dataloading in test phase 1, thereby forcing the value of the scan-inputpath (SI) to “1” no matter what the value of the scan path (S) is. Thus,phase_cntl1 overwrites the original test pattern value supplied by thetest pattern generator. However, during all other test phases,phase_cntl1's value is “0”, so the value of the scan path (S) is passedunchanged to the scan cell 800.

Likewise, as shown in FIG. 9B, when a “0” constraint is needed, testlogic 902B may include an inverter 910B to invert the test phase triggersignal (here, phase_cntl2) on the scan-override path 908B and a gate906B implementing the AND function. The inverted test phase triggersignal and the gate 906B force the value of the scan-input path (SI) to“0” when the test phase trigger signal has the value “1”.

These constraints may also be alternatively implemented, such as byusing other logical gate arrangements. Moreover, there are cases whereit is desirable for a scan cell to have different constraints duringdifferent phases of a test. In such cases, for example, both AND and ORgates may be used, as shown in the exemplary embodiment of FIG. 9C. If ascan cell is to assume the same constraint through several phases of atest, corresponding phase-control signals may be, for example, ORedtogether in test logic 902C at a gate 904C that produces the scan-inputpath (SI) of the scan cell 800A. Moreover, the test phase trigger signalis not limited to the value “1”, as illustrated here. These values andlogic implementations should not be construed as limiting in any way, asthe desired functionality and advantages of the disclosed architecturecan be accomplished using architectures that operate with differentvalues. All such variations, however, are considered to be within thescope of the present disclosure.

As compared to MTPI, the disclosed embodiments of theconstrained-scan-cell architecture maintain the constructive nature offault-coverage convergence while minimizing or eliminating performancedegradation due to control-point insertion within the functional pathsof the CUT. A fault-coverage plot of a typical 4-phase run of anexemplary embodiment of the disclosed architecture is shown in FIG. 10.Most easy-to-test faults discovered by pseudo-random patterns generatedby the PRPG (e.g., an LFSR) are detected in test phase 0. Constrainedscan cells are used in each of the subsequent phases to target subsetsof pseudo-random-resistant faults.

V. Exemplary Embodiments of a Method for Selecting Observation Pointsand Constrained Scan Cells

The selection of observation points and control points may beimplemented in a constructive manner, similar to that of multi-phasetest point insertion (MTPI). For example, any of the techniquesdisclosed in U.S. Pat. No. 6,070,261, which is incorporated herein byreference, may be utilized in whole or in part.

FIG. 11 is a flowchart of an exemplary general method 1100 for insertingobservation points 1108 and constrained scan cells 1110 into anintegrated circuit design utilizing the concepts discussed above. Themethod 1100 may be carried out by an EDA tool that is resident in acomputer system (such as computer system 102) and may be implemented insoftware, hardware, or a combination of both. For example, an EDA toolmay perform the disclosed method on an integrated circuit designcomprising a representation of the integrated circuit stored in one ormore data structures or databases on computer-readable media (e.g., anetlist or HDL file). The flowchart in FIG. 11 shows only one exemplaryembodiment and should not be construed as limiting in any way.

The exemplary method 1100 shown in FIG. 11 receives as inputs a set ofparameters, such as the number of random patterns, the number of phases,target-fault coverage, the maximum number of constrained scan cells perphase, and the maximum number of observation points, though many otherinputs can also be used in alternative embodiments.

At process block 1102, a benchmark signature for the integrated circuitdesign is established by applying a number of test patterns to a logicsimulation of the integrated circuit design to obtain the expected,fault-free response. At process block 1104, the test patterns areapplied during fault simulations, and an undetected fault list iscreated that lists the faults undetected so far by the test patterns.

At process block 1106, it is determined if this is the first test phase;if so, then at process block 1108 observation points are selected. Withreference to FIG. 7, observation points 702 allow the detection offaults, although they produce a pattern change within the CUT, whosefault pattern does not propagate to an output. In an exemplaryembodiment, observation points are inserted by adding an output leadfrom the chosen location to a location where one or more faults areobservable. Observation points are useful as not only do they oftenallow detection of otherwise-undetectable faults, but also have lowoverhead. Further, observation points typically influence circuitperformance less than conventional control points inserted into the corelogic of the CUT. In one embodiment, for instance, only one additionalfan-out within the CUT is used to observe a node. An XOR tree may alsobe used to compact observation points and feed them into an existingscan cell or into a new scan cell. An exemplary XOR tree is described inV. S. Iyengar and D. Brand, “Synthesis of Pseudo-Random Pattern TestableDesigns,” Proc. of Int'l Test Conf., pp. 501-508 (1989). Observationpoints are desirably, although not necessarily, enabled through all testphases.

In one exemplary embodiment of the method 1100, the “best” observationpoints are selected iteratively. The “best” observation point maydefined as the one associated with the node at which the greatest numberof faults can be seen with at least a user-defined detection probability(e.g., the detection threshold “DTh”). Other criteria can also be usedto determine the “best” observation point. Observation points continueto be iteratively selected—the next-best observation point is located,and so on—until a selected observation point fails to meet auser-specified minimum-benefit-per-cost (MBPC) criterion. Otherimplementations may insert a set number of observation points based onDTh, or utilize different criteria.

If not at the first test phase, then, at process block 1112, using theundetected fault list generated at process block 1104, it is determinedif current fault coverage is at or exceeds a user-defined target faultcoverage. If so, then the method 1100 terminates. Otherwise, the method1100 continues at process block 1110 where constrained scan cells areselected. At process block 1114, it is determined if there are stilltest phases left (e.g., according to a user-specified limit). If so, thecurrent test phase is updated, and, as shown at process block 1104,fault simulation is again performed using all of the constrained scancells and observation points selected up to this point to determine thelist of still-undetected faults.

In one exemplary embodiment, the process of selecting constrained scancells performed at process block 1110 involves iteratively selectingsets of constrained scan cells that can detect the most faults in theundetected fault list 1104. An exemplary embodiment of this process isfurther examined in the discussion accompanying FIGS. 12A and 12B.

In general, one of the objectives of the exemplary embodiment is towinnow the constrained-scan-cell candidates to a reasonable number ofscan cells. Indeed, it is typically undesirable to list all scan cellsas constrained-scan-cell candidates. For example, consider a modestdesign with 10,000 scan cells. As each scan cell in this illustrationhas two possible constraints (“0” or “1”), there will be a total of2×10,000=20,000 constrained-scan-cell candidates, a number that isrelatively large from a computing perspective. In the MTPI scheme,control points are selected sequentially; the best is found, then thesecond-best, and so on. One might consider doing the same thing in theconstrained-scan-cell scheme, which can be conceptually viewed as usingcontrol points at the scan output of scan cells. A control point inMTPI, however, is a 1/0-failing node. When a control point is inserted,it will at least activate a stuck-at-1 or a stuck-at-0 fault at acontrol-point site, and will further facilitate propagation of thefaults in the fan-in region of its parallel inputs. By contrast, when asingle constrained scan cell is set, it is difficult for the constrainedscan cell to facilitate detection of those hard-to-control orhard-to-observe faults.

For example, and with reference to FIG. 7, scan cells 716, 718, 720, and722 (scan cells SC₁-SC₄) are used to control the value at control point706. Only when all four scan cells output the value “1” into the inputpaths 708, 710, 712, and 714 of the node 704 will the value at thecontrol point 706 be driven to “1”.

Therefore, setting a single scan cell (e.g., SC₁) to “1” while leavingthe other three scan cells unconstrained will have little chance offorcing the value of “1” at the control point 706, as it would requirethe other three scan cells (e.g., SC₂-SC₄) to all randomly be assigned“1”s by the test pattern generator. In a typical circuit design, thereare many instances where several scan cells must be constrainedsimultaneously to produce the desired effect at the control point.Accordingly, it is typically undesirable to consider constrained scancells one by one.

Instead, it is desirable to select scan cells in sets, known as “cubes”or “justification cubes”, that can control the value of a specificcontrol point. For example, with reference to FIG. 7, the four scanvalues “1, 1, 1, 1” make up the cube to produce the value “1” at thecontrol point 706. Cube size is typically not constrained except by thenature of the fault patterns to be inserted into the CUT and the designof the CUT.

FIGS. 12A and 12B show an exemplary procedure for choosing constrainedscan cells utilizing the concepts discussed above. The flowchart 1200shows only one exemplary embodiment of implementingconstrained-scan-cell selection and should not be construed as limitingin any way.

At process block 1202, probabilistic fault simulation is performed toobtain a propagation profile. Using the undetected fault list generatedat process block 1104, probabalistic fault simulation computes for eachnode in the CUT a list of undetected faults that propagate to thatnode—each logic gate generally comprising a node. It also computes eachfault's associated detection probability.

In some embodiments, probabilistic fault simulation is performed asfollows: first, a pattern probability is determined; the patternprobability is based on the actual set of “0's” and “1's” that arepropagated to each node and lists the successive values held by the nodeand how long each was held. From the pattern probability, the signalprobabilities at the nodes of the CUT are computed. The signalprobability is the percentage of time that a specific input to a nodeholds the values “1” and “0”. For each fault on the undetected faultlist and at the node associated with the fault, a variable isinitialized to the signal probability of that node. Forward faultpropagation is performed to find the detection probability of this faultat possible forward control nodes. For each node, the detectionprobability of each fault that can be observed at the node is summed toform a fault-detection value. When the fault-detection value at a nodefalls below a detection threshold, the forward fault propagation ishalted. The value of the detection threshold can be determined byconsidering factors such as the phase duration and the desired detectionconfidence, and can be varied across different test phases. Thisdetection probability information is referred to generally as thepropagation profile.

At process block 1204, control-point candidates are chosen. In oneexemplary embodiment, control point candidates with low controllabilityare chosen; that is, those nodes which require a specific set of valuesnot generated by the pseudo-random patterns on their inputs to properlytest them. With reference to FIG. 7, for example, the node 704 can bethought of as having low controllability because each of its four inputpaths 708, 710, 712, 714 must have the value “1” to drive its outputvalue to “1”. Another exemplary method chooses control point candidatesby selecting 1/0-failing nodes with estimates E0/E1, which are greaterthan a minimum acceptable value.

At process block 1206, a control point candidate is selected from amongthe control point candidates. At process block 1208, a backwardjustification is performed to obtain one or more justification cubes forthe selected control point candidate. Here, the term “justification”means determining the input values at upstream scan cells necessary toobtain a desired value at a given control point. For example, referringagain to the circuit illustrated by block diagram 700 in FIG. 7, duringa test phase, when the value “1” is inserted on each of the input paths708, 710, 712, 714, to the AND gate node 704 upstream from the controlpoint 706, the control point will be driven to the value “1” in afault-free circuit. This has the effect of testing the AND condition ofthe node 704. The value “1” in each of the four scan cells 716, 718,720, and 722 (scan cells SC₁-SC₄) forms the justification cube forcontrol point 700. Justification as described above can be performed bya number of known methods.

At process block 1210, the set of scan cells within the cube are checkedagainst current scan-cell constraints for overlap. If there is nooverlap, at process block 1214, the cube is identified as a cubecandidate (sometimes referred to herein as a “justification-cubecandidate”); otherwise, as shown at process block 1212, it is discarded.

For a given control point, more than one possible justification cubemight exist that can be used to drive the control point to a desiredvalue. Thus, at process block 1206, multiple justification cubes may bedetermined. In certain embodiments of the disclosed technology, one ofthe possible justification cubes is chosen at random to be thejustification cube evaluated at process block 1210. In otherembodiments, however, multiple possible justification cubes for a givencontrol point are evaluated at process block 1210 in order to select ajustification cube that does not overlap with previously selected scancell constraints for a specific test phase.

At process block 1216, a determination is made whether there are morecontrol point candidates. If so, these candidates, in turn, obtain theirjustification cubes 1208 and are checked for overlap 1210. As a result,a number of cube candidates are determined that do not conflict withcurrent scan-cell constraints. With reference to FIG. 12B, once allpossible cube candidates are determined, at process block 1218, a cubecandidate is selected, and at process block 1220 the cube candidate isevaluated to obtain its actual benefit, as is more thoroughly describedin FIG. 13. This benefit is assessed by some predetermined procedure orevaluation parameter, and can be a parameter that indicates thedetectability (or observability) of faults within the CUT when thescan-cell constraints of the cube candidate are set, or can be measuredusing some other method.

At process block 1222, it is determined if there are more cubecandidates. If so, the process continues at process block 1218 with eachcube candidate selected in turn and at process block 1220 where eachcube candidate is evaluated. Once all cube candidates have beenevaluated, at process block 1224, the cube candidates are sorted bytheir evaluation values, known here as their ActCubeBPC (actual cubebenefit parameter calculation). At process block 1226, the cubecandidate with the highest ActCubeBPC is chosen. In process block 1228it is determined if the cube candidate with the highest ActCubeBPC (orwith a ActCubeBPC meeting a specified criteria) meets a benefit-per-costcriterion. If so, at process block 1230, it is selected, and thecorresponding scan-cell constraints are added to the specific testdesign. In some embodiments, the ActCubeBPC criteria concerns locatingthe control point cube that produces the greatest number of faults thatpropagate to observable circuit locations. In an exemplary embodiment,if the cube candidate with the highest ActCubeBPC does not meet the BPCcriteria, then the remaining justification cubes do not produce enoughbenefit to be included in the circuit under test, and so this test phaseis considered completed.

At process block 1232, it is determined whether sufficient justificationcubes have been selected for a given test phase. If so, the processbreaks; if not, the process continues at process block 1226, aspreviously discussed. In some implementations, constrained scan cellsare selected until a user-defined number or percentage of undetectedfaults has been detected. In other implementations a user-defined numberof constrained scan cells is chosen for each phase. In yet otherimplementations, a combination of the above methods is employed. Thoseof skill in the art will discern other methods of selecting controlpoints, justification cubes, and observation points.

Returning to FIG. 11, it should be noted that the procedure discussed inFIGS. 12A and 12B is repeated for each test phase, after updating theundetected fault list using a fault simulation wherein the just-selectedscan cell constraints are activated. Thus, the fault simulation atprocess block 1104 incorporates all of the previously chosen constrainedscan cells to arrive at a revised fault list that includes only thosefaults that have yet to be found. As can be seen with reference to FIG.10, the fault coverage improves with each added test phase.

An exemplary method 1300 shown in the flowchart of FIG. 13 can beutilized to evaluate cube candidates as shown at process block 1220. Theexemplary method 1300 represents a particular embodiment that expandsthe exemplary methods described above and should not be construed aslimiting in any way. Instead, the method may be modified in arrangementand detail without departing from the scope of the disclosed technology.For example, certain acts described may be omitted in particularembodiments, and certain acts may be performed in an order differentthan that shown.

At process block 1302, a scan cell in the cube selected at process block1220 is checked against previously assigned scan-cell constraints. Atprocess block 1304, if the scan cell has not yet been constrained, acorresponding constraint value is assigned to the scan cell. This can bethought of conceptually as temporarily inserting test logic between thechosen scan cell and the appropriate test phase trigger signal. Atprocess block 1306 it is determined if more scan cells in the cubecandidate need to be constrained. If so, the process continues atprocess block 1302, repeating until all scan cells in the cube have beenappropriately constrained. Otherwise, the process continues at processblock 1308.

The usefulness of this cube is evaluated by determining which faultswill be detected if it is used. At process block 1308, with the cubeconstraints in place, logic simulation of the circuit is performed usingthe current list of undetected faults. This obtains the signal andpattern probability under the scan-cell constraints. At process block1310, probabilistic fault simulation is used to obtain a propagationprofile which gives for each node the probability that apreviously-undetected fault can now be found. One or more faults thathave yet to be detected are simulated, and the probability that theywill be detected at each node is determined. These individual detectionprobabilities at each node are summed so that the undetected fault has asingle probability value that is the total chance in the CUT that thefault will be detected—the fault detection probability. In one desirableembodiment, this process is repeated for every fault on the undetectedfault list. At process block 1312, the fault detection probability ofeach fault on the undetected fault list are themselves summed, giving asingle value that represents the overall chance of this specific cubedetecting any faults. This value is referred to here as the Actual CubeBenefit Property Calculation (ActCubeBPC).

At process block 1314, the scan-cell constraints assumed for the cubeevaluation are cleared, and the evaluation of the selected cubecandidate ends. Returning to FIG. 12B, it can be seen that eachjustification cube has its ActCubeBPC determined and that thejustification cubes are selected based on their ActCubeBPC value.

In contrast to control-point-candidate evaluation in MTPI, it is notnecessary to perform the analytical techniques that compute asignal-probability change or pattern-probability change in the fan-outregion of the control point. Instead, these procedures can be replacedwith logic simulation of a predetermined number of pseudo-randompatterns. Even though the analytical techniques may, in some cases, beperformed faster than logic simulation, the techniques are not accurateenough to reflect the signal-probability change in the fan-out region ofa cube candidate. Indeed, the fan-out region of a cube candidate can bemuch larger than that of a control point in core logic, restricting theusefulness of the analytical technique. Certain embodiments of thedisclosed method, however, may still use the analytical technique.

VI. Experimental Results

In this section, experimental results obtained from using an exemplaryembodiment of the disclosed BIST methods are presented. The exemplaryembodiment utilized in the tests was substantially identical to themethods presented in FIGS. 11-13 discussed above. The exemplaryembodiment was applied to several pseudo-random-resistant ISCASbenchmark circuits and three large industrial designs. All test-coverageresults are based on a single stuck-at fault model. In all experiments,32,000 pseudo-random patterns were applied in order to obtain a faircomparison. For BIST schemes with multiple phases, the number ofpatterns in each phase was equally distributed. For instance, in a4-phase BIST run, 8,000 patterns were allocated for each phase; while an8-phase run utilized 4,000 patterns per phase.

Table 1 shows the results from five pseudo-random-resistant ISCASbenchmark circuits. For purposes of the tests conducted, it was assumedthat boundary scan had been applied to the circuits so that data couldbe scanned into primary inputs and scanned out from primary outputs.

TABLE 1 Experimental Results for ISCAS Benchmarks 32k pseudo- 32k, 4ph32k, 8ph random Exemplary BIST MTPI Exemplary BIST MTPI Circuit F. ECPs/OBs F.E. CPs/OBs F.E. CPs/OBs F.E. CPs/OBs F.E. C2670 95.78 27/4100.0 1/5 100.0 — — — — C7552 97.67  34/11 99.52  7/11 99.53  61/1199.58  8/11 99.55 S9234 94.80  67/21 99.83 15/30 99.73  90/30 99.9815/30 99.83 S15850 97.84 167/30 99.94 17/30 99.89 202/30 99.90 17/3099.87 S38417 97.03 239/30 99.79 28/30 99.62 333/30 99.84 20/30 99.55

In Table 1, the second column lists the fault efficiency (F.E.) obtainedfrom the 32,000 pseudo-random patterns tested. The following columnsshow both 4-phase and 8-phase BIST runs using the exemplary embodimentof the disclosed BIST scheme and MTPI. The composite number ofconstrained scan cells (or control points for MTPI) and the observationpoints are listed in subcolumns “CPs/OBs”, while the corresponding faultefficiency is listed in subcolumns “F.E.” As shown by Table 1, when thenumber of observation points is kept the same for the exemplary BISTscheme and MTPI, the exemplary BIST scheme can achieve comparable orhigher fault efficiency than MTPI. However, the constrained-scan-cellcount is much higher, which is to be expected as multiple constrainedscan cells are often set to produce a desired fault test value. Table 1also shows that the number of observation points for c2670 and s9234 isnot equal for the exemplary BIST scheme and MTPI in the 4-phase run,even though the same number of observation points was asked for in bothschemes. This variance was caused by using a slightly modified versionof the observation-point-selection method when computing the observationpoints for the MTPI run. A similar result was observed with theindustrial designs. For all ISCAS benchmark circuits, the ATPG faultefficiency was at or near 100%, indicating that the exemplary BISTscheme is able to achieve ATPG or near-ATPG coverage.

Table 2 shows the results from three large industrial designs.

TABLE 2 Comparison of Different Schemes on Industrial Circuits 32k, 4ph32k, 8ph 32k MTPI MTPI p.rand ATPG Exemplary F.E. Exemplary F.E.Circuits Gates SCs PIs POs F.E. F.E. F.E. (cost) (cost) F.E. (cost)(cost) IND1 24,424 503 58 109 93.23 97.17 96.71 97.01 96.97 97.08 (54/100)  (26/100)  (68/100)  (30/100) IND2 103,682 5,638 322 531 92.8898.17 97.40 97.92 97.78 97.97 (191/200) (122/200) (414/200) (152/200)IND3 410,880 10,821 930 964 93.58 99.54 97.93 98.17 98.23 98.25(492/527) (117/558) (898/800) (136/800)

The second through the fifth columns of Table 2 list basic informationconcerning the industrial designs. In particular, the second column is agate count. which ranges from about 24,000 to about 410,000; the thirdcolumn is the number of scan cells from about 500 to about 10,000; andthe fourth and fifth columns are the number of primary inputs andprimary outputs, respectively. The fault efficiency (F.E.) obtained fromthe 32,000 pseudo-random patterns is given in the sixth column. Theseventh column indicates ATPG Fault Efficiency with a BIST constraint.Specifically, when performing a built-in self test, X sources have to bebounded in order to avoid unknown states. Thus, in order to generatetest patterns that were applicable in the BIST environment, this sameconstraint was applied to ATPG test generation. Moreover, the F.E.obtained by ATPG with the BIST constraint is indicative of the upperbound of BIST coverage. Columns eight and ten show F.E.'s and costs fora 32,000 pattern 4-phase and 8-phase run, respectively, using theexemplary BIST scheme. The cost inside the parentheses is a compositevalue of constrained scan cells (or control points for MTPI) andobservation points. For comparison, the ninth and eleventh columns listthe results from corresponding 4-phase and 8-phase runs using MTPI. Dueto an updated version of the observation point selection method, thenumber of observation points produced by the exemplary embodiment isslightly lower than that of MTPI even though the same number of controlpoints were requested at the start of the procedure.

Compared to the same size of 32,000-pseudo-random-pattern testing, theexemplary BIST scheme is able to improve fault efficiency by 4% to 5%using nonzero observation points. For all three designs, coverage can beimproved by increasing the number of phases. However, more constrainedscan cells (and thus more phase-control signals) are required to achievethe coverage gain, indicating a tradeoff between better coverage andless hardware overhead. It can also be observed from Table 2 that, insome instances, MTPI performs slightly better than the exemplary BISTscheme. For example, in the 8-phase BIST run, shown in the eleventhcolumn, with nonzero observation points, MTPI had 97.08% faultefficiency for the first independent run (IND1) versus 96.97% for theexemplary BIST scheme, as shown in column 10. For the second independentrun, MTPI's fault efficiency was 97.97%, while the exemplary embodimentshowed a fault efficiency of 97.78%. The third independent run gave afault efficiency of 98.25% for the MTPI procedure, while the exemplaryembodiment had a fault efficiency of 98.23%. These differences are quitesmall, amounting to 0.11%, 0.19%, and 0.02%, respectively. For thebiggest design, IND3, which has more than 400,000 gates, the coveragedifference between the two schemes is only 0.02%.

One possible reason MTPI has slightly higher test coverage than theexemplary BIST scheme is that by inserting control points into the corelogic, MTPI is able to perturb the fault list and make some redundantfaults testable. As to hardware overhead, Tables 1 and 2 indicate thatwhen the number of observation points is set the same for both MTPI andthe exemplary BIST scheme, the number of constrained scan cells used inthe exemplary BIST scheme is about 2 to 7 times that of the number ofcontrol points use in MTPI. For IND1, for example, when 100 observationpoints are used in a 4-phase BIST run, the ratio of constrained scancells in the exemplary BIST scheme to control points in the MTPI schemeis 54 to 26. This ratio becomes 898 to 136 for IND3 when 800 observationpoints are used in an 8-phase run. This largeconstrained-scan-cell-to-control-point ratio, however, only results inan increase of 762 constrained scan cells (898−136=762), which accountsfor only 0.18% of the total 410,000 gates. Thus, even though theexemplary BIST scheme may result in additional BIST hardware, theincrease is within an acceptable range.

To examine whether the exemplary BIST scheme provides improved testcoverage, test generation was performed with BIST constraints. Theresults of ATPG testing are listed in the seventh column of Table 2 andindicate an upper bound of BIST coverage. For IND1, fault efficiencyobtained by the ATPG method was 97.17%, whereas the fault efficiency forthe exemplary BIST scheme was 96.97%; for IND2, ATPG was 98.17%, whereasthe exemplary BIST scheme was 97.78%; and for IND3, ATPG was 99.54%,whereas the exemplary BIST scheme was 98.23%. These results indicatethat the exemplary BIST scheme is able to achieve close to ATPG coveragewith acceptable hardware overhead.

VII. Exemplary Network Environments

Any of the aspects of the technology described above may be performed ordesigned using a distributed computer network. FIG. 14 shows one suchexemplary network. A server computer 1400 can have an associated storagedevice 1402 (internal or external to the server computer). For example,the server computer 1400 can be configured to designconstrained-scan-cell components according to any of the embodimentsdescribed above (e.g., as part of an EDA software tool, such as adesign, verification, or simulation tool). The server computer 1400 maybe coupled to a network, shown generally at 1404, which can comprise,for example, a wide-area network, a local-area network, a client-servernetwork, the Internet, or other such network. One or more clientcomputers, such as those shown at 1406, 1408, may be coupled to thenetwork 1404 using a network protocol. The work may also be performed ona single, dedicated workstation, which has its own memory and one ormore CPUs.

FIG. 15 shows that a database containing design information (e.g., anetlist or an HDL database) may be updated to include design informationfor a constrained-scan-cell architecture according to any of theembodiments disclosed herein using a remote server computer, such as theserver computer 1400 shown in FIG. 14. In process block 1502, forexample, the client computer sends design data relating to a circuithaving one or more constrained scan cells to be tested using any of thedisclosed testing methods and/or using any of the disclosedconstrained-scan-cell architectures. For instance, the client computermay send a netlist or other EDA design database. In process block 1504,the design data is received and loaded by the server computer. Inprocess block 1506, the circuit defined by the design data is updated toinclude a BIST architecture according to any of the disclosedembodiments. New design data representing the updated circuit design canthen be created. This new design data can be stored, for example, as anupdated version of the design database or as one or more separatedatabases. In process block 1508, the server computer sends the updateddesign data to the client computer, which receives the updated data inprocess block 1510. It should be apparent to those skilled in the artthat the example shown in FIG. 15 is not the only way to update a designdatabase to include the relevant design data. For instance, the designdata may be stored on a computer-readable medium that is not on anetwork and that is sent separately to the server. Or, the servercomputer may perform only a portion of the design procedures.

Having illustrated and described the principles of the illustratedembodiments, it will be apparent to those skilled in the art that theembodiments can be modified in arrangement and detail without departingfrom such principles. For example, in one embodiment, one or morefunctional paths in the core of the CUT utilize constrained scan cells,whereas the remainder of the core logic utilizes test points under anMTPI scheme. Further, many of the software aspects of the embodiment maybe implemented in hardware, and many of the hardware aspects may beimplemented in software. Also, many of the disclosed methods can bearranged in a different order to achieve the same end result. Thoseskilled in the art will recognize that the disclosed embodiments can beeasily modified to accommodate different situations and structures.

In view of the many possible embodiments, it will be recognized that theillustrated embodiments include only examples and should not be taken asa limitation on the scope of the invention. Rather, the invention isdefined by the following claims. We therefore claim as the invention allsuch embodiments and their equivalents that come within the scope ofthese claims.

1.-32. (canceled)
 33. A circuit, comprising: circuit logic; one or morescan chains coupled to the circuit logic, the one or more scan chainscomprising scan cells operable in at least a scan mode and anoperational mode; and test logic coupled to a scan path of at least twoof the scan cells, the test logic being configured to load the at leasttwo of the scan cells with either a fixed value or a pseudo-random valuewhile the scan cells are operating in the scan mode.
 34. The circuit ofclaim 33, wherein the test logic is not directly coupled to the circuitlogic.
 35. The circuit of claim 33, further comprising a pseudo-randompattern generator coupled to the test logic, the pseudo-random patterngenerator producing the pseudo-random value.
 36. The circuit of claim33, wherein the pseudo-random pattern generator is a linear feedbackshift register (LFSR).
 37. The circuit of claim 33, further comprising aphase decoder coupled to the test logic, the phase decoder at leastpartially producing the fixed value.
 38. The circuit of claim 37,further comprising a shift counter having an output signal that islogically coupled with an output signal of the phase decoder, the shiftcounter being configured to control when the fixed value is loaded bythe test logic into the at least two of the scan cells.
 39. The circuitof claim 38, wherein the shift counter is configured to load the fixedvalue during a last shift cycle of the scan mode.
 40. The circuit ofclaim 33, further comprising an observation point in the circuit logic,the observation point having a value indicative of the presence of afault whose value does not otherwise propagate to circuit logic outputs.41. One or more computer-readable media storing computer-executableinstructions for causing a computer system to design or simulate acircuit, the circuit comprising: circuit logic; one or more scan chainscoupled to the circuit logic, the one or more scan chains comprisingscan cells operable in at least a scan mode and an operational mode; andtest logic coupled to a scan path of at least two of the scan cells, thetest logic being configured to load the at least two of the scan cellswith either a fixed value or a pseudo-random value while the scan cellsare operating in the scan mode.
 42. The one or more computer-readablemedia of claim 41, wherein the test logic of the circuit is not directlycoupled to the circuit logic.
 43. The one or more computer-readablemedia of claim 41, wherein the circuit further comprises a pseudo-randompattern generator coupled to the test logic, the pseudo-random patterngenerator producing the pseudo-random value.
 44. The one or morecomputer-readable media of claim 43, wherein the pseudo-random patterngenerator is a linear feedback shift register (LFSR).
 45. The one ormore computer-readable media of claim 41, wherein the circuit furthercomprises a phase decoder coupled to the test logic, the phase decoderat least partially producing the fixed value.
 46. The one or morecomputer-readable media of claim 45, wherein the circuit furthercomprises a shift counter having an output signal that is logicallycoupled with an output signal of the phase decoder, the shift counterbeing configured to control when the fixed value is loaded by the testlogic into the at least two of the scan cells.
 47. The one or morecomputer-readable media, of claim 46, wherein the shift counter isconfigured to load the fixed value during a last shift cycle of the scanmode.
 48. The one or more computer-readable media of claim 41, whereinthe circuit further comprises an observation point in the circuit logic,the value at the observation point being indicative of the presence of afault whose value does not otherwise propagate to circuit logic outputs.49. One or more computer-readable media storing computer-readable designinformation for a circuit, the circuit comprising: circuit logic; one ormore scan chains coupled to the circuit logic, the one or more scanchains comprising scan cells operable in at least a scan mode and anoperational mode; and test logic coupled to a scan path of at least twoof the scan cells, the test logic being configured to load the at leasttwo of the scan cells with either a fixed value or a pseudo-random valuewhile the scan cells are operating in the scan mode.
 50. The one or morecomputer-readable media of claim 49, wherein the test logic is notdirectly coupled to the circuit logic.
 51. The one or morecomputer-readable media of claim 49, wherein the circuit furthercomprises pseudo-random pattern generator coupled to the test logic, thepseudo-random pattern generator producing the pseudo-random value. 52.The one or more computer-readable media of claim 51, wherein thepseudo-random pattern generator is a linear feedback shift register(LFSR).
 53. The one or more computer-readable media of claim 49, whereinthe circuit further comprises a phase decoder coupled to the test logic,the phase decoder at least partially producing the fixed value.
 54. Theone or more computer-readable media of claim 53, wherein the circuitfurther comprises a shift counter having an output signal that islogically coupled with an output signal of the phase decoder, the shiftcounter being configured to control when the fixed value is loaded bythe test logic into the at least two of the scan cells.
 55. The one ormore computer-readable media of claim 54, wherein the shift counter isconfigured to load the fixed value during a last shift cycle of the scanmode.
 56. The one or more computer-readable media of claim 49, whereinthe circuit further comprises an observation point in the circuit logic,the value at the observation point being indicative of the presence of afault whose value does not otherwise propagate to circuit logic outputs.